Testing and measuring certain parametrics electronic products is a crucial part of the manufacturing process. This is particularly the case with today's complex products, in which even the smallest hardware defect can cause serious malfunctions. Integrated circuits are widely used because they offer a high functionality per unit of cost. Today's system-on-silicon and core-based design styles drive the integration of logic and memory within a single device. An increasing percentage of the silicon area in a complex IC is embedded memory. To achieve the economies necessary in modern integrated circuit manufacturing, it is necessary to minimize both the cost of the raw circuit as well as the cost of testing and measuring certain parametrics. However, testing of the embedded memories within these complex ICs is increasingly difficult. Adding test access to the embedded memories increases design size and complexity and in some cases increases cost. As products, however, become more complex, it becomes difficult to use traditional external testing methods. This is the case because the integrated-circuit are operating at increasing frequencies. In addition, testing equipment has bandwidth and performance limitations.
Circuit time delay is the amount of time necessary to process input information and make it available for further processing at the output of the circuit. The circuit time delay measure provides the information necessary for integration with other circuits. More particularly, access time is the time that a memory device, such as dynamic random access memory (DRAM) and static RAM (SRAM), takes to locate a single piece of information and make it available to the computer for processing. Access time for a DRAM ranges from 50 to 150 nanoseconds. While the access time for the SRAM can be as low as 600 picoseconds. Access time is the primary measurement used to sort devices because it is the best indicator of the die process parameters. It is an absolute requirement that an accurate measurement of the memory access time be obtained, particularly, in view of the continuous trend towards decreasing the system cycle time coupled to the design of high speed SRAM macros having themselves a reduced memory access time.
Built-In Self Test (BIST), which moves critical test and measurement functions inside chips, are commonly used to measure access time. BIST uses scanning technology to provide the stimulus-generation and response-processing capabilities necessary to test and measure parametrics for complex logic structures and embedded memory. An example of access time measurement using Array Built-In Self Test (ABIST) is described in U.S. Pat. No. 5,386,392 entitled "Programmable High Speed Array Clock Generator Circuit for Array Built-In Self Test Memory Chips" which is incorporated by reference herein.
Herein a clock distribution scheme is considered, yet, it is difficult if not impossible to test the memory of the SRAM macro having such short system cycle time and make accurate memory access time measurements because of the unacceptable imprecision caused by uncontrollable clock signal skews. This is particularly true in the ABIST manufacturing sub-mode where the imprecision inherent to the clock distribution scheme originates from a variety of factors such as: tester limitations, width variations of the clock signals generated by the tester, off-chip line delays caused by the lines between the tester and the chip, chip internal clock distribution networks, etc. In addition, calibration of the clock signals generated by the tester is required for state of the art SRAM macros. This calibration is process dependent and thus must be done for each chip lot. The calibration is achieved by estimating the internal delays after accurate kerf measurements. As a result, it is expensive and time consuming to perform an accurate memory access time measurement in an ABIST manufacturing sub-mode because it requires high performance and expensive testers. However, this skew also exists in the ABIST system sub-mode. It is caused by the chip internal clock distribution network and by mismatches in the internal chip path delay thereof. For each clock signal, the mismatch results from physical wiring layout imbalances and device differences between the driver circuits that buffer the clock signals, which in turn results in layout and process dependency.
A preferred embodiment of the ACG circuit optimized for the ABIST manufacturing sub-mode of the reference cited includes two delay lines having, two 2-way AND gates, and three inverters. It further includes a 2-way AND gate. The clock signal is applied to the input terminal which is connected to a first input of AND gate and first inverter. The output of first inverter is connected to the input of first delay line, whose output is connected to the second input of first AND gate and to the first input of a second AND gate via a second inverter and a second delay line. The clock signal is applied to the second input of a second AND gate by a connection or optionally via a third delay line. The ungated clock signal available at the output of the first AND block is gated at third AND gate by gating signal generated by the ABIST unit when the clock signal CACG at a first output terminal is inhibited. The CSACG signal is available through the third inverter at a second output terminal. The BACG and the SACG signals are generated by the second AND gate and are available at a common third output terminal.
This embodiment is optimized for the ABIST manufacturing sub-mode when the macros are individually tested on a serial basis by the external tester which can precisely control the width of the clock signal, and which is the same for all the macros within the chip. Circuit thus allows an accurate memory access time measurement simply by varying the clock signal pulse width when the chip is tested during the ABIST manufacturing sub-mode, and it is thus easy to determine its operating limits. However, whereas a precise control of the pulse width is relatively simple in a manufacturing environment thanks to the tester, it becomes quite difficult in the system environment.
Another possible approach to measuring access time in embedded memories is to connect the control, address, and data lines of the memories to external pads of the integrated circuit. Multiplexer blocks are implemented within the integrated circuit to connect the embedded memories either to the external pads for testing or to internal buses for standard circuit operation. A drawback to this approach is that the extra bus lines and pads increase the size of the semiconductor die and the extra pads increase the number of pins required of the tester. The cost of the tester is generally roughly proportional to the number of pins. Since the trend is toward wide memories of increasingly large capacity in modern ICs, the number of extra buses and pads required can frequently exceed one-hundred, which represents a prohibitive cost burden. In addition, the delay from the bondpad driver is typically larger than the delay of the SRAM.
Another approach includes storing the outputs of an SRAM in a register. Problems arise, however, when the clock frequency increases simultaneous to the timing edge for the register. As a result, the clock period is shortened which is available to sample the data. Varying the frequency of the register while recording samples mingles the timing information from the memory and device logic where the information is not separable or distinguishable.
There is a need for an built-in circuit delay measurement apparatus that may be used in a variety of applications, including memory devices, such as SRAM and a DRAM.